A deep trench (DT) gating effect may exist in an array of eDRAM devices and is a prominent leakage mechanism that reduces the retention time of eDRAM devices. For example, in an array of eDRAM devices, each device may comprise a storage cell (e.g., a deep trench capacitor) and a gate (e.g., a FET). The storage cell of one device may electrically couple with the SOI island in which a FET of an adjacent device is formed. This capacitive coupling between the storage cell of one eDRAM and the SOI island of a FET of an adjacent eDRAM weakly turns on the surface at the back or bottom corner of the SOI island that the adjacent FET is formed on, which creates a leakage current in the adjacent FET. The leakage current causes the adjacent eDRAM to lose its charge, e.g., the information stored in its storage cell. Such leakage necessitates more frequent refreshing which is undesirable for a number of reasons, including the fact that more frequent refreshing consumes more power.
A technique for reducing DT gating is to increase the spacing between the storage cells and the gates of adjacent devices. However, increasing the spacing between devices goes against the constant drive in the industry for reducing the size of integrated circuits. Another way to address DT gating is by performing halo implants, through-gate implants, and/or well implants at the FET. However, such implant techniques result in doping the entire backside and/or entire sidewall of the SOI island in which the FET is formed, and such over-doping can negatively affect device performance in an undesired manner.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.